Since the demand and the increasing of various portable devices, the data volume on the communication links is rising exponentially, requiring the wireline communication systems, especially the data center providing high-speed, accurate and stable data transmission solutions. Considering as the core of data center equipment and facilities, optical communication and high-speed wireline communication systems request drastic improvement in speed, power and stability, while in all its blocks, the clock and data recovery circuit determines the clock quality of the total receiver end and the jitter and bit error rate (BER) of the received data.
Traditional CDRs usually adopt III-V processes likes GaAs, which is deemed as high-speed and low-noise material and perfect for radio frequency circuit. However, its high supple voltage decides its low-grade performance in power consumption. Meanwhile, the improvement in CMOS process and the increasing in its characteristic frequency, derived from the reduction in character size, makes it possible to implement low-power, high-performance, high-speed circuit by CMOS process.
There are two main categories for conventional CDRs: linear and bang-bang (BB). While linear CDRs exhibit excellent recovered clock jitter due to the lower quantization jitter, the input data is supposed to drive the logic circuits directly, which demands high input swing. Besides, the locking time and jitter tolerance of linear CDRs are typically inferior due to the smaller loop bandwidth. Alternatively, bang-bang CDRs utilize oversampling to determine the edge transition location with slicer, reducing the input data swing to about 50 mV. This binary judgment results in a faster locking process and larger jitter tolerance, but unfortunately degrades quantization jitter and bit-error rate (BER). It is challenging to adopt the advantages of both architectures and eliminate their weaknesses.